Neue HPSDR Version von Pavel, gesehen von Sigi, DH1KLM

I’ve just checked the spurious signals using sdr_transceiver_hpsdr and PowerSDR mRX PS.

spurious_signal_1

The frequency of the tune signal is 21.2000 MHz.

The frequency of the spurious signal is 39.0527 MHz.

(39.0527 – 21.2000) * 7 = 124.9689 MHz
(39.0527 – 21.2000) * 8 = 142.8216 MHz

I’d say that 124.9689 significantly differs from 125. Normally, the frequency deviation of the on-board 125 MHz oscillator is within 2-3 ppm.

However, 142.8 MHz is also present in the sdr_transceiver_hpsdr configuration. This frequency is generated by the ZYNQ PS PLL and is used to clock most of the FPGA logic.

Here is how ZYNQ PS PLL generates 142.8 MHz:

33.333 * 30 / 7 = 142.8557 MHz

I don’t know what is the frequency deviation of the on-board 33.333 MHz oscillator. I’ll try to measure it.

Owner

pavel-demin commented 4 days ago

I’ve built a modified FPGA configuration for sdr_transceiver with all the FPGA logic clocked from the 125 MHz oscillator. The TX signal is much cleaner now.

sdr_transceiver before the modification:
trx_test_1

sdr_transceiver after the modification:
trx_test_2

Here is a link to the new FPGA configuration:

https://www.dropbox.com/sh/5fy49wae6xwxa8a/AADoCQp9SvGXvEssxuA6uUeJa/dac_test/sdr_transceiver_test.bit?dl=1

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